A. Field of the Invention
This invention relates to programmable digital data processors, with particular emphasis on those processors which process vector instructions. More specifically, it relates to those data processors which utilize a pipelined approach to the processing of these vector instructions.
In the development and advance in data processing systems there has been an ever-increasing emphasis on increasing the data processing rate. This desire for higher speed has led us to different approaches to accomplish this. One approach was to use separate processing elements to overlap the execution of instructions. This, of course, has automatically brought with it the need of asynchronous operation, since the separate processors accomplished their individual tasks in different time periods. This asynchronous operation of the multiple processing elements caused memory access conflicts, since many times there were concurrent requests for the same memory location. This invention then specifically relates to a system for organizing the memory of scientific data processing system using the pipeline approach.
B. Prior Art
Increases in computing rates have been achieved through advances in physical technologies relating to the hardware and hardware functioning. The advent of integrated circuitry gave rise to circuit components operable at very fast computing rates, and capable of performing complex functions while remaining economically feasible. Access and cycle time of memories has also been markedly decreased.
In addition to the changes and developments in the hardware, there have been continuing advances in the organizational architecture of data processing system that provide for ever-increasing utilization of the various data processing components. While many examples of optimization of utilization of the components comprising the data processing systems can be described, attention will be directed to the concept of increasing data processing rates by providing for an overlap of macro instruction execution.
It has been known for some time that instructions in data processing systems that basically provide for the steps of instruction procurement and instruction decoding, instruction operation, and storage of results, could be overlapped such that once an existing instruction was procured from the memory and the current instruction passed into execution, the memory would be available for accessing for the next instruction. This allowed overlapping of the instructions primarily based upon the availability of access to the memory unit. This type of instruction overlapping was most common in the data processors that involved so-called hardwired instruction repertoire and control.
Later developments lead to data processing systems that utilized a repertoire of macro instructions each of which performed some predetermined function in the data processing system. The macro instructions, characteristically at the user level, are programmed and stored in a memory unit for retrieval and execution as the particular program progresses. In systems of this type, a control store is utilized for storing sets of micro instructions, each one of the stored sets relating to an associated one of the macro instructions. The execution of a selected macro instruction is accomplished by the execution of each one of the micro instructions in the corresponding set thereof. In the execution of each micro instruction, control signals are produced and fed to the Arithmetic Processor to control the processing of data in accordance with the controls specified by each of said micro instructions. In current technology the control store would be either a Random Access Memory (RAM) or a Read Only Memory (ROM). However, the RAM has the relative advantage of providing versatility for the control store in that the sets of micro instructions may be altered by simply writing new control micro instructions into the control memory.